Latch circuits are an essential building block for most digital circuits and are used in a variety of digital integrated circuits. For instance, gate arrays and standard cell libraries devote large numbers of their cells to latch circuit designs. Furthermore, most latch circuits included in a library have minor variations, such as a scan input or set/reset options.
It is well known that the speed at which a digital circuit operates is determined by its worst case data path. Latch delays can be a large portion of the worst case delay due to their high proclivity of use in digital designs. Accordingly, by concentrating on reducing latch delays, it is possible to significantly increase speeds of digital systems.
Latches often form the basis of flip flops, such as a D-type flip flop. The D-type flip flop (as well as many other flip flop designs) is formed in two distinct sections called a master section and a slave section. The master section receives and stores data coupled to the flip flop input during one phase of the clock cycle. The data is shifted from the master section to the slave section during the other phase of the clock cycle. The slave section stores and provides the data at the flip flop outputs. Such flip-flops are implemented with a relatively large amount of gates, and therefore use relatively large amounts of power especially at high frequencies.
The power consumption of flip flops in frequency dividers operating at high frequencies can be undesirable. This power consumption occurs mainly as a result of the numerous transistors switching on or off during every clock cycle. Accordingly, latch circuits that selectively clock data only when new data has been detected at their inputs have been developed. However, such latch circuits use delay circuitry in the clock signal path to create phase shifted or delayed clock signals that can lead to undesirable power consumption.
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